first of all, happy new year ! I just moved to Bangkok for several days now (for University of course, KMITL if you doubt). Anyway lets go back to the main story.
Couple months ago, I’ve been playing around with iCESugar Nano board. FINALLY, I entered FPGA world. The board looks like this :
It based on Lattice iCE40LP1K-CM36. One nicey thing about this FPGA is that there’re open source synthesizer (thing that turns hardware description language into actual logic gates and stuffs) and routing tool (thing that auto route logic connections likes auto route in EAGLE CAD). These tools are “Yosys” and “Nextpnr-ice40”.
The reason that I got this FPGA is because of my MN15439A VFD display that not only require triple data line SPI but also Gradient Pulse control signal that doesn’t behave like “normal PWM” wave. So, my first project is the display controller : (Shutter sync is pain in the a$$).
Well, right now the 8 levels (0-7) grayscale is working. But BRAM (Block-RAM) as display buffer always leaves weird artifacts on the display. It’s turned out to be the BRAM timing / cycle problem. After I wrote address (I want to read) to BRAM, data came out “reliably” at 3rd clock cycle…
The iCESugar nano is nice. But it cost me $18.2 and has onboard programmer which is acceptable but it doesn’t utilize the FPGA to the maximum (Only 14 pins available, 2 reserved for UART that can’t disable and I’ll tell you later why, 1 reserved for clock and I’ll tell you later too why I also don’t happy about this).
The creator of iCESugar nano called the onboard programmer based on APM32 as “iCELink”. It capable of Drag-N-Drop programming (flash onboard SPI NOR), provide UART com between PC and your FPGA and Generates Clock signal to FPGA. However, UART can’t be disabled. It took 2 pins away from this board that I could’ve use to do something else. Also the clock generator only running at 12MHz by default, It’s true that I can change the speed via their binary program that com over HID. But it lack of data retention and there’s no point that FPGA changes main clock speed on the fly.
I open issue on GitHub and suggest them to implement the clock speed retention. But now It’s just them that they will do it or not. But at the same time. I’m also working on the open source firmware to replace their closed source. It will capable of Drag-N-Drop programming, clock generation + retention, Toggleable UART and CRAM programming mode (send bit stream directly to FPGA without flashing the external SPI NOR). But I don’t have the original firmware so I don’t risk bricking my “iCELink”
From all of the issues above. I led me to design my own board using same FPGA. I dubbed it “iCEHAX40” :
This is my first time to did a very advanced PCB design involving BGA chip. I tried to keep it 2 layers because of cost and simpleness. The boards are fabbed by OSHPark. The technique that I can (almost) fan out all pads is called “DRC violating”. It’s not special thing, It’s just don’t follow rule. Which is really bad and I will show you why.
Everything has a limit, PCB manufacturer too. The minimum trace spacing and width of 2 layers that OSHPark “reliably” produce is 6mil. But there’s people went sub-4mil and get reliable result. I did tried too. Traces don’t lifted off the board, but the nature of BGA that suppose to use “vias in pad” technology that cost $300+ over PCBway forces me to fan out on single layer. Due to really thigh space. I didn’t design them good enough so I ended up with bridges.
As you can see from pics above. Even though I tried and thought that the trace sits in the very middle space between 2 pads. Some yes. Some nope.
All 3 boards yield almost same result, some have same short path, some don’t. I already fixed the design by being more careful and use .25mil grid to helps centering the traces. Also I at the same time, try the 3.5mil on 2 layers manufacturing. I’ve seen someone be able to get down to 3mil (!) on 4 layers. So I thing 2 layers might still fine at 3.5mil.
The 3.5mil boards went to fab 2 days ago (2022/01/14). I’ll update the experiment after month or so. So, stay tuned for the next blog pose ;D